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Amstrad PPC Technical Reference Manual. This manual provides a comprehensive description of the Amstrad PPC.
General information about the PPC and the delivered. Amstrad PPC User Instructions. This manual is intended to satisfy the needs of advanced developers.
PPC6. 40 and. PPC5. Note that all address constants in this document are hexadecimal.
In. addition hexadecimal quantities are noted with small letter 'h' terminator. Address quantities are not.
Values are. presented in hexadecimal form when they are logically bit oriented quantities. The CPU is a low power 8. Megabyte memory. addressing capability (See Figure 1. MHz. The CPU is connected to an on- board 1. S timing cycles (T- States) per access resulting in a 5. S memory cycle for. The CPU is also connected on an on- board 8 bit I/O and memory.
MHz clock, which in turn connects to an external. Operations on the 8- bit bus automatically incur 1. S wait. states as follows: Operation. Wait States. Bus Cycle. Memory)4. 1. 0 μS1.
Memory)1. 22. 0 μS8- bit (I/O)6. S1. 6 to 8- bit convert (I/O)1. SThe CPU is configured to run in maximum mode and the instruction set may be. Numeric Data Coprocessor.
The. 8. 08. 7 BUSY output is connected directly to the 8. NOT TEST input. The main board memory consists of 6. K bytes of system RAM with parity.
K bytes of system ROM without parity checking. The 6. 40. K byte user RAM starts at CPU memory address 0. FFFF. Note that the PPC5. K bytes installed memory ending at. FFFFh and the address space from 8.
FFFFh may be extended. K byte blocks (up to the 6.
K maximum). The 1. K byte address space from A0. BFFFF is reserved for video. CPU programs. The PPC Internal Display Adapter (IDA) uses the 6. K byte address range.
B0. 00. 0 to BFFFF. The segmentation of this memory range is dependent. See section 1. 1. External display.
The 1. 92. K byte address space from C0. EFFFF is reserved for external. ROM address space. Hard Disk controllers use the range from C8. C9. FFF. Additional hard disk controllers may also use the area from CA0.
CD0. 00. The PPC test board uses the ROM area from E0. E7. FFF. The 1. 6K byte system ROM is at FC0. FFFFF and contains the Resident. Operating System (ROS) firmware. The 4. 8K byte address range from F0. FBFFF is reserved for ROM space expansion. The 1. 6K byte ROS area address.
ROS ROM repeats four times in the. F0. 00. 0 to FFFFF address range. MEMORY LAYOUT0. 00. ON- BOARDDYNAMIC RAM6. K. Byte. System Memory 9.
FFFFA0. 00. 01. 28. K. BYTESVIDEO DISPLAY BUFFERS BFFFF1. M. BYTEADDRRANGEC0.
K. BYTES EXPANSION ROMS EFFFF F0. K BYTES ROS ROM BLOCK REPEATS6. K Byte. System ROMarea. FBFFFFC0. 00. 16. K. BYTES (ROS) RESIDENT OPERATING SYSTEM ROMFFFFF The interfaces on the main board occupy the 8. I/O addresses as follows: ADDRESS(hex)OUTPUT USEINPUT USE0. F8. 23. 7 DMA Controller.
DMA Controller. 01. FDo Not Use. Do Not Use. Interrupt control.
Interrupt control. FDo Not Use. Do Not Use. PIT Load Count (0- 2)8. PIT Read Count (0- 2)0. PIT Load Mode. Undefined. FDo Not Use. Do Not Use.
No Effect. Port A - Keyboard Code or System Status 1. Port B - System Control. Port B - (Readback)0. No Effect. Port C - System Status- 2. No Effect. Do Not Use. Write System Status- 1.
Do Not Use. 06. 5Write System Status- 2. Do Not Use. 06. 6System Reset. Do Not Use. 06. 7 - 0. FDo Not Use. Do Not Use.
RTC Address. Do Not Use. RTC Data. 14. 68. RTC Data. 07. 2 - 0. Do Not Use. Do Not Use. Reserved. Reserved.
Do Not Use. Do Not Use. AReserved. Reserved. B - 0. 7FDo Not Use.
Do Not Use. 08. 0Do Not Use. Do Not Use. 08. 1DMA Page Register Ch 2. Do Not Use. 08. 2DMA Page Register Ch 3. Do Not Use. 08. 3DMA Page Register Ch 0,1. Do Not Use. 08. 4 - 0. FDo Not Use. Do Not Use.
A0. NMI Mask Control. Do Not Use. 0A1 - 0. BFDo Not Use. Do Not Use. C0 - 0. FFReserved. Reserved. 2F8 - 2. FFModem UART Tx. Data/Control Modem UART Rx. Data/Control. 37.
Printer Data Latch. Printer Data Latch. Do Not Use. Printer Status. APrinter Control Latch.
Printer Control Latch. B - 3. 7FDo Not Use. Do Not Use. 3B0 - 3. B7. Mono Mode CRTCRegisters.
Mono Mode CRTCRegisters. B8 - 3. BFMono Mode Control. Registers. Mono Mode CRTCRegisters. D0 - 3. D7. Colour Mode CRTCRegisters. Colour Mode CRTCRegisters.
D8 - 3. DFColour Mode Control. Registers. Colour Mode Control. Registers. 3F0 - 3. F1. Do Not Use. Do Not Use. F2. Drive Selection. Do Not Use. 3F3. Do Not Use. Do Not Use. 3F4. Do Not Use.
FDC Status. 3F5. 76. FDC Data. 76. 5 FDC Data. F6 - 3. F7. Do Not Use. Do Not Use. 3F8 - 3. FFCOM1 8. 25. 0 UART Tx. Data/Control. COM1 8.
UART Rx. Data/Control. The 8. 08. 6 CPU I/O addresses on the expansion bus are as follows: ADDRESS(hex)USE2. FExternal Game Control Interface. External Bus Expansion Unit. FReserved. 27. 8 - 2.
FExternal Printer Port. F0 - 2. FFReserved. FExternal Prototyping Card. FExternal Hard Disk Controller. FExternal SDLC Serial RS2.
C Port. 3A0 - 3. AFReserved. B0 - 3. BBExternal Monochrome VDU Controller. BC - 3. BFPrinter Port. C0 - 3. CFExternal Graphics Controller. D0 - 3. DFExternal Colour/Graphics Controller. I/O address above 0.
FFh, if accessed, wrap around and are mapped onto. FFh. External cluster controllers at 0. B9. 0h- 0. B9. 3h.
I/O addresses. 0. The Amstrad PPC supports four DMA channels on the system board, using an. DMA controller and programmable page registers to extend its addressing. M byte processor address range.
Each channel. is able to transfer data in blocks of up to a maximum of 6. K bytes within a page. The DMA channels are for 8- bit data transfers between (8- bit) I/O devices and. In peripheral (slave) mode, CPU I/O address lines A0 - A3 are connected.
See section 3. 5). The DMA controller CLK is driven at 4. MHz (+/- 0. 1%). In master mode. DMA transfers on channels 1,2 and 3, one wait state is added resulting. DMA bus cycle of 1.
S. Channel 0 transfers have a four- clock. S. The DMA channel request signals are as follows: DMA Channel.
USE0. 82. 53 Timer/Counter OUT1 output - for memory refresh. Spare for use by expansion bus. Used by external SDLC Serial Port. Floppy Disk Controller DRQ output. Available on the expansion bus. Spare for use by expansion bus.
Used by external Hard Disk Controller. DMA channels 1, 2 and 3 can address the entire 1. M byte addressing range of.
CPU through the use of their associated DMA page registers. There are. three DMA registers, one each for channels 1 through 3. Each page register. K byte pages in the 1. M byte. address range DMA transfers are to occur. The page registers are static so. K byte addressing occurs at page boundaries.
The DMA page register bit assignments are as follows: Bit. Output Use. 7- 4.
Not Connected. 3Address bit A1. Address bit A1. 81. Address bit A1. 70.
Address bit A1. 6Following a reset, system (ROS) initialisation firmware (in the ROS) sets up the. DMA controller for channel 0 (dynamic refresh) operation as follows: Function.
Initialised State. Word Count. 64. K Transfers. Mode. Register. Read. Autoinitialise. Increment. Single Mode. Command. Register. Disable Memory to Memory.
Enable Controller. Normal Timing. Fixed Priority.
Late Write. DREQ Active High. DACK Active Low. Mask.
Register. Clear Channel 0 Mask Bit. After power- up or system reset the DMA page registers are undefined and are. ROS firmware and all 8. Following industry compatibility, memory to memory DMA is not supported on. PPC. It is prohibited due to timing considerations.
Nine levels of hardware interrupt are provided for in the system by the. CPU Non Maskable Interrupt (NMI) and by an 8. A- 2 Interrupt Controller. All. levels including NMI, are maskable under software control. CPU I/O address line A0 is connected conventionally so that the command. The SP/EN pin is. The interrupt levels are assigned as follows: Level.
Assigned Function. NMIMemory Parity Error and 8. NDP INT output. 0. Timer/Counter Out. Keyboard Scan Code Receiver. Real Time Clock IRQ output.
Available on the expansion bus. May be used by Enhanced Graphics Adapter. Used by Modem Serial Port (COM2)and external SDLC Serial Port. Available on the expansion bus. Primary Serial port (COM1).
Available on the expansion bus. Used by external SDLC Serial Port. Hard Disk Controller.
Available on the expansion bus. Floppy Disk Controller INT output. Available on the expansion bus.
Parallel Printer Port. Available on the expansion bus. Used by external Printer Port (secondary) and Printer. Port (ternary) on external Monochrome VDU Controller. Following a reset, the initialisation firmware in the ROS sets the 8.
Interrupt Controller to operate as follows. Single (not cascaded),Normal fully nested (not special),Edge- triggered,Buffered mode - slave,Normal EOI (not auto),Fixed priority - level 0 highest, level 7 lowest. The system (ROS) firmware initialises the 8. IRQ0 through IRQ7 appear in the CPU interrupt vector space at.
NMI is configured to CPU. The NMI Mask Control is a write only register at I/O address 0. A0h and allows. the CPU non- maskable interrupt (NMI) input to be enabled or disabled by. The Bit assignments are as follows: Bit. Output Use. 7Enable NMI.
Not Connected. Following a reset NMI is disabled. NMI can be connected to the 8.
NDP, the on- board memory parity check. I/OCHCK (I/O Channel Check). Three programmable timer/counters are provided at I/O Addresses 0.
Programmable Interval Timer (PIT) device. They are defined as.
Counter. Use. 0General Purpose Timer. Used by DMA channel 0 (for dynamic ram refresh). Tone Generation for Speaker. The 8. 25. 3 timers are configured as follows: Function.
Configuration. CLK 0,1,2. MHz +/- 0. 1% (5.
GATE 0,1. Always 'ON'. GATE 2. Controlled via Port B (System Control Channel). Speaker Modulate output. OUT 0. Interrupts on 8. PIC IR0 input. OUT 1. Requests on 8. 23.
DMA DREQ0 input. OUT 2. Logical 'AND' with Port B (System Control Channel). Speaker Drive output.
Also goes to Port C. System Status- 2 Channel) as an input. Following a reset, the system initialisation firmware in the ROS programs. PIT for counter 1 (dynamic ram refresh) operation as a rate generator. S. There are no restrictions. Two system status input channels and four output channels are provided. Ports A, B and C emulate a pre- programmed 8.
PPI device. They.
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Similar to the repair manuals available on CD, this manual provide you with visual and step by step instructions to make flawless repairs to your electronic items. A must have for anyone who owns AMSTRAD SRX1. SRD4. 00 SATELLITE RECEIVER. Helps you with. Setting up the Receiver with your TV.
Setting up the Receiver with your TV and Video Recorder. Setting up the Receiver with Scart/Peritel Equipement. Aligning the Dish.
Operating the Receiver. Scrambled the Broadcasts.
Parental Lock and Recording Lock. Rear Controls and Sockets.
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